An important component in an all digital phase locked loop (ADPLL), which is used as an illustrative application of the invention, is the time to digital converter. The function of the TDC is to measure and quantize the time differences between a frequency reference clock FREF and the clock edges of the digitally controlled oscillator (DCO) output. This is done to compute the digital fractional part of the variable phase. In the frequency/phase detector, the differentiated timestamps and variable phase are subtracted from a frequency command word (FCW). The frequency error samples are then accumulated to create the phase error samples which are then filtered by the ADPLL loop filter(s).
In its simplest and most power efficient form, the TDC circuit is constructed as an array of inverter delay elements and flip-flop latches. The digital fractional phase is determined by passing the DCO oscillator clock (CKV) through the chain of inverters such that each inverter output produces a clock delayed by the amount of the propagation delay of an inverter with respect to the previous inverter output. The latches in the TDC are clocked at the reference frequency rate (FREF) and constitute a pseudo-thermometer code. This code is decoded to generate a quantized fractional phase between CKV and FREF in terms of inverter delays. Note that the fractional notion stems from the fact that the inverter delay is much smaller than either of the two clocks between which the phase is being computed.
The TDC quantization noise is broadband and additionally depends on the characteristics of the jitter of the DCO output clock. The ADPLL transfer function from TDC to DCO output, however, is low-pass in nature. Therefore, in-band TDC noise is one of the sources of phase noise at the output of the ADPLL. In fact, this can become one of the dominant noise contributors as the ADPLL loop bandwidth is widened. An analytical study of the ADPLL phase noise spectrum contributors at the RF output reveals that the TDC phase noise contribution can be minimized by either improving the TDC timing resolution, increasing the sampling rate or both.
Three potential internal sources of noise include: (1) the oscillator, (2) corruption of the reference frequency, and (3) the TDC operation of calculating the timing delay difference. It is noted that other than these three sources of internal phase noise, the system, due to its digital nature, is relatively immune from any time-domain or amplitude-domain perturbations and does not contribute to the phase noise. The TDC quantization noise can potentially produce undesirable effects such as idle tones (due to limit cycles) in the ADPLL output spectrum. Furthermore, this can cause degradation of root mean squared (RMS) phase error, close-in spectrum, etc.
The TDC quantization noise can cause significant performance degradation when the RF clock edges are varying slowly with respect to the FREF clock edges. In such cases, TDC essentially provides information-less constant readout. This is the case for integer-N channel operation, N being the ratio between CKV and FREF frequencies. For an integer-N channel, each FREF cycle will contain approximately same integer cycles of the RF clock.
The operation of the TDC, even though it possesses digital characteristics, generates phase noise due to fact that the FREF and DCO clock inputs possess jitter in the continuous time domain. The TDC contributed error comprises several components including raw quantization errors, TDC non-linearity errors (such as integral and differential non-linearity) and random errors due to thermal and device hot carrier effects. Of these three mechanisms, the TDC quantization noise is the most dominant in the current CMOS process technology. As mentioned above, the TDC phase error degradation is particularly worse (i.e. may possess unwanted spikes) when caused by ill-conditioned TDC behavior for channels that are integer-N multiples of the reference frequency.
Thus, there is a need for a robust mechanism that is capable of reducing the TDC quantization noise in feedback circuits, such as ADPLL circuit. In the case of an ADPLL, the mechanism should be capable of reducing the TDC quantization noise for both integer as well as non-integer channels.